1. Field of the Invention
This disclosure relates to semiconductor devices, and more particularly, to a method of manufacturing a fin field effect transistor.
2. Description of the Related Art
Recent rapid development in the information and communication field, and a popularization of information media such as computers, have brought about a rapid progress of semiconductor devices. A high-integration of semiconductor devices has brought about research activity for various methods of reducing a feature size of individual devices formed on a substrate while increasing performance of the devices.
In such methods a field effect transistor (FET) is increasingly used to improve integration of devices based on a silicon semiconductor technique and a CMOS (Complementary Metal Oxide Semiconductor) technique, which have a prominent production presence. A scaling-down of a general planar field effect transistor in conformity with the high-integration of the devices results in a lowered performance or reliability of the devices. Thus three-dimensional structures, such as a vertical transistor, have been proposed instead of a planar type structure.
As an example of these structures, a fin field effect transistor (fin FET) has been proposed. The fin FET has a characteristic vertical structure of a transistor body that resembles a fin shape like a fish dorsal, which is disclosed in U.S. Pat. No. 4,996,574 or 6,635,923, etc. A conventional fin FET employs an SOI (Silicon On Insulator) type silicon substrate where a general silicon substrate and a single crystal silicon layer, or a single crystal silicon film having a predetermined thickness, are bonded with each other, with an interposed insulation layer such as silicon oxide. The conventional fin FET is formed in such a way that a channel formation fin active region is vertically protruded with a predetermined height and line width on the insulation layer. Also, a gate electrode obtained by forming a gate insulation layer on a surface of the fin active region is formed crossing the fin active region and surrounding it. A sectional face of the fin active region protruded from the insulation layer becomes a width of channel, and a line width of the gate electrode crossing the fin active region becomes a length of channel. Such a fin FET, according to a conventional technique, can use an entire face of protruded portions as channels, thus having a remarkably increased channel width effect as compared with a conventional planar fin FET. Since a channel length is not reduced in a fin FET, according to a conventional technique, by a scaling-down of a device formation region as compared with a general transistor, a narrow channel effect caused by a channel width reduction can be prevented. To reduce a width of protruded portion, a channel depletion layer formed in the gate region may be partially depleted or fully depleted. There is thus a channel conduction increase effect.
However, a fin FET manufacturing method according to a conventional technique has the following problems.
First, production costs of the SOI type silicon substrate is high, which results in increased manufacturing costs of the device with decreased productivity. This is the case of using an SOI type silicon substrate in which an insulation layer is formed between a bottom silicon substrate and a silicon layer when forming a fin FET on an insulation layer.
Second, performance of the device falls by a floating body effect caused in a triple gate fin FET manufacturing method using an SOI type silicon substrate according to a conventional technique. This is because a transistor body is not connected with a substrate by a characteristic aspect of the device formed on the SOI type silicon substrate, thus an electron-hole pair is concentrated on a surface near an insulation layer when a channel is formed on the body.
Third, for an SOI type silicon substrate it is difficult to control the height of an interlayer dielectric or a shallow trench insulator for partially exposing the fin active region. Clearly, it is advantageous to use bulk silicon substrate instead of an SOI type silicon substrate to form a fin active region.